懂的话我就发代码跟帖了~~

你倒是发

Verilog 代码：用的状态机
module spi4(clk100M,reset,CSB_N,sdo,sclk
);
input clk100M;
input reset;
output CSB_N;
output sclk;
output sdo;
reg CSB_N;
reg sclk;
reg sdo;
reg [2:0] cntclk;
always @(negedge clk100M)
if(reset)
begin
sclk<=1'b0;
cntclk<=3'd4;
end
else
begin
cntclk<=cntclk+1'b1;
sclk<=cntclk[2];
end


parameter data1 =16'b0010000000111000;
parameter data2 =16'b0100101000111101;
parameter data3 =16'b0100111101011100;
reg [3:0] cnt_data1;
reg [3:0] cnt_data2;
reg [3:0] cnt_data3;
reg [3:0] state_data;
always @(negedge clk100M)
begin
if(reset)
begin
state_data<=4'd0;
end
else
case(state_data)
4'd0 : begin
CSB_N <=1'b1;
sdo<= 1'b1;
cnt_data1<=4'd15;
cnt_data2<=4'd15;
cnt_data3<=4'd15;
state_data<=4'd1;
end
4'd1: begin
if(cntclk==3'd4)
begin
CSB_N<=1'd0;
sdo<=data1[cnt_data1];
if(cnt_data1==4'd0)
begin
cnt_data1<=4'd15;
state_data<=4'd2;
end
else
cnt_data1<=cnt_data1-1;
end
end
4'd2: begin
if(cntclk==3'd4)
begin
CSB_N <=1'b1;
state_data<=4'd3;
end
end
4'd3: begin
if(cntclk==3'd4)
begin
CSB_N <=1'd0;
sdo<=data2[cnt_data2];
if(cnt_data2==4'd0)
begin
cnt_data1<=4'd15;
state_data<=4'd4;
end
else
cnt_data2<=cnt_data2-1;
end
end
4'd4: begin
if(cntclk==3'd4)
begin
CSB_N<=1'b1;
state_data<=4'd5;
end
end
4'd5: begin
if(cntclk==3'd4)
begin
CSB_N<=1'd0;
sdo<=data3[cnt_data3];
if(cnt_data3==4'd0)
begin
cnt_data3<=4'd15;
state_data<=4'd6;
end
else
cnt_data3<=cnt_data3-1;
end
end
4'd6: begin
if(cntclk==3'd4)
begin
CSB_N<=1'b1;
end
end
endcase
end


endmodule